FPGA Implementation of Low Power Decompressed Real Time Video Segmentation

Saritha.K, R.Lakshmipathy

Abstract: Background identification is common feature in video system .This project deals with the hardware implementation of the Gaussian mixture model algorithm of decompressed real time video. As this project is mainly focused on receiver end, decompression plays an important role. At the receiver side only compressed video will be captured. So the original video should be got back through decompression. Inverse Discrete Cosine Transform is used here, since it is effective and less noise interfered technique. Also scaling of image is also done so that the video which is taken by the camera will be compactable with the display devices. So this project in cooperates three processes called segmentation decompression and scaling with low power consumption. The reduction in power is proved using Quartus.

Keywords: Computer vision, Image motion analysis, Object detection, Subtraction techniques, DCT.

Title: FPGA Implementation of Low Power Decompressed Real Time Video Segmentation

Author: Saritha.K, R.Lakshmipathy

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

Research Publish Journals

Vol. 2, Issue 2, April - June 2014

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FPGA Implementation of Low Power Decompressed Real Time Video Segmentation by Saritha.K, R.Lakshmipathy