Abstract: The optimization of power dissipation has become one of the barriers for scaling of MOSFET to catch up ITRS roadmap. The life time of battery operated devices may be reduced due to the power. In CMOS nano regime technologies, power dissipation plays an important role. In most of the digital systems adder lies in the vital path that enhance the propagation delay of the system. This paper proposes a new three transistor based design with significant area and power savings for ripple carry adder. A comparative study and analysis of various power minimization techniques for ripple carry adder have been presented in this paper and the study shows that three transistor based design is more effective than other existing techniques. The result is validated by Eldo SPICE Simulator in Mentor Graphics at 0.35um CMOS process technology.
Keywords: TSMC0.35, Power Optimization, 3T XOR gate, Full Adder, Pseudo NMOS Logic, Ripple Carry Adder.
Title: Power Optimization for Ripple Carry Adder with Reduced Transistor Count
Author: Manju Bala, Neeraj Gupta, Priti Singh
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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